On one hand, a metal oxide semiconductor field effect transistor (MOSFET) built on a silicon-on-insulator (SOI) substrate typically offers advantages over a MOSFET with comparable dimensions that is built on a bulk substrate by providing a higher on-current and lower parasitic capacitance between the body and other MOSFET components. On the other hand, a MOSFET built on an SOI substrate tends to have less consistency in the device operation due to “history effect,” or “floating body effect,” in which the potential of the body, and subsequently, the timing of the turn-on and the on-current of the SOI MOSFET are dependent on the past history of the SOI MOSFET. Furthermore, the level of leakage current also depends on the voltage of the floating body, which poses a challenge in the design of a low power SOI MOSFET.
The body of an SOI MOSFET stores charge which is dependent on the history of the device, hence becoming a “floating” body. As such, SOI MOSFETs exhibit threshold voltages which are difficult to anticipate and control, and which vary in time. The body charge storage effects result in dynamic sub-threshold voltage (sub-Vt) leakage and threshold voltage (Vt) mismatch among geometrically identical adjacent devices.
As in any MOSFET, the source, the body, and the drain of a SOI MOSFET form a parasitic bipolar transistor. Since the body of the SOI MOSFET is electrically floating, the base of the parasitic bipolar transistor is also floating. The SOI MOSFET with the floating body may have a breakdown voltage that is about 8˜10 times less than the breakdown voltage of a MOSFET having otherwise identical components and having a grounded base. The floating body may have a detrimental effect on reliability of the SOI MOSFET.
Several methods have been provided in the prior art to alleviate the deleterious effect of the floating body on the breakdown voltage of the SOI MOSFET. In one approach, the body of an SOI MOSFET is electrically grounded so that the base of the parasitic bipolar transistor is also grounded. In another approach, the electric field in the drain may be reduced by employing a lightly doped drain (LDD) structure. In yet another approach, the lifetime of minority carriers are increased in the body to decrease the gain of the parasitic bipolar transistor. These techniques are in general beneficial to reduction of the floating body effect in general by either reducing the impact ionization rate or by efficiently removing a floating charge from the body.
Each of the above approaches, however, has certain drawbacks. Body contact structures for grounding the body tend to require a relatively large area. Also, the efficacy of such body contact structures depends on the size of the SOI MOSFET. Further, such devices are inherently asymmetric, and may not be used for applications that require symmetry of the device such as a pass gate transistor in a static random access memory (SRAM) cell. The lightly doped drain structure increases resistance of the drain extension region and reduces the on-current of the device. Reduction of the lifetime of the minority carriers increases leakage current in an off-state of the SOI MOSFET.
In view of the above, there exists a need to increase a breakdown voltage of an SOI MOSFET without accompanying adverse effects on device performance.
Specifically, there exists a need to increase the breakdown voltage of the SOI MOSFET without requiring an additional device area, without reducing an on-current, and without increasing an off-current.